Exemplary embodiments of the present invention relate to semiconductor designing technology, and more particularly, to a semiconductor integrated circuit.
In general, packaging technology for a semiconductor integrated circuit has made a continuous progress to decrease size and increase mount reliability. To obtain high performance despite miniaturization of electrical/electronic devices, technologies for stack package have been developed.
In the semiconductor industry, “stack” means piling up at least two semiconductor chips or packages vertically. When the stack package is applied to a semiconductor memory device, the semiconductor memory device may have more than twice as much memory capacity as the memory capacity that may be realized through a typical semiconductor integrated circuit fabrication process. Also, since the stack package is advantageous in terms of increasing mount density and efficiency in using a mount area as well as increasing the memory capacity, the stack package technologies are drawing attention.
Stack package may be fabricated through a method of stacking individual semiconductor chips and then packaging the stacked semiconductor chips at once or a method of stacking packaged individual semiconductor chips. The individual semiconductor chips of the stack package may be electrically connected through metal wire or a through chip via. Here, a stack package using a through chip via has a structure where a through chip via is formed within semiconductor chips and the semiconductor chips are physically and electrically connected to each other vertically through the through chip via. Here, the through chip via may be a through silicon via (TSV).
FIG. 1 illustrates a typical through chip via.
Referring to FIG. 1, a semiconductor chip C for a stack is formed by forming a via in a semiconductor chip A and forming a through chip via B by filling the via with metal. A semiconductor integrated circuit is formed by stacking a plurality of such semiconductor chips C. The fabricated semiconductor integrated circuit is typically referred to as a three-dimensional (3D) stack package semiconductor integrated circuit.
FIG. 2 illustrates a conceptual diagram of a typical semiconductor integrated circuit.
In the specification, the technology of the present invention is described by taking an example of two semiconductor chips having two through chip vias stacked one on the other is described.
Referring to FIG. 2, a semiconductor integrated circuit 100 includes first and second semiconductor chips 110 and 120 stacked vertically, and first and second through chip vias 130 and 140 which penetrate through the first semiconductor chip 110 and transfer first and second control signals SIGNAL_TSV1 and SIGNAL_TSV2 outputted from the first semiconductor chip 110 to the second semiconductor chip 120. Here, the second semiconductor chip 120 may not have any through chip via. This is because, when diverse circuits are formed on the surfaces of the upper portions of the first and second semiconductor chips 110 and 120, the second semiconductor chip 120 may receive diverse signals outputted from the first semiconductor chip 110 through a pad formed on the surface. When more than three semiconductor chips are stacked, the lowermost semiconductor chip may not have such a through chip via.
Meanwhile, the first semiconductor chip 110 overlying the second semiconductor chip 120 is often referred to as a master chip. The master chip buffers an external signal applied from the outside, e.g., a controller, and controls the second semiconductor chip 120 through the first and second through chip vias 130 and 140. The second semiconductor chip 120 controlled by the master chip is often referred to as a slave chip.
The master chip 110 includes first and second output circuits 112 and 114 for outputting first and second control signals SIGNAL_TSV1 and SIGNAL_TSV2 for controlling the slave chip 120. Here, the first and second output circuits 112 and 114 are disposed on the upper surface of the master chip 110.
The slave chip 120 includes first and second input circuits 122 and 124 for receiving the first and second control signals SIGNAL_TSV1 and SIGNAL_TSV2. Here, the first and second input circuits 122 and 124 are disposed on a surface of the slave chip 120.
One end of the first through chip via 130 is coupled with the first output circuit 112 and the other end of the first through chip via 130 is coupled with the first input circuit 122. The first through chip via 130 interfaces the transfer of the first control signal SIGNAL_TSV1 outputted from the first output circuit 112 to the first input circuit 122. One end of the second through chip via 140 is coupled with the second output circuit 114 and the other end of the second through chip via 140 is coupled with the second input circuit 124. The second through chip via 140 interfaces the transfer of the second control signal SIGNAL_TSV2 outputted from the second output circuit 114 to the second input circuit 124. In FIG. 2, a semiconductor integrated circuit is shown to have the first and second through chip vias 130 and 140. However, a semiconductor integrated circuit in FIG. 2 may include hundreds or thousands of through chip vias.
In the semiconductor integrated circuit 100 having the above-described structure, the master chip 110 and the slave chip 120 exchange the first and second control signals SIGNAL_TSV1 and SIGNAL_TSV2 through the first and second through chip vias 130 and 140. With such a configuration, the semiconductor integrated circuit 100 may reduce current consumption and signal delay.
However, the conventional semiconductor integrated circuit 100 raises the following concerns.
The first and second through chip vias 130 and 140 serve as interface through which the first and second control signals SIGNAL_TSV1 and SIGNAL_TSV2 are transferred between the master chip 110 and the slave chip 120. Here, each of the first through chip via 130 and the second through chip via 140 serves as the interface for one signal, that is, either the first control signal SIGNAL_TSV1 or the second control signal SIGNAL_TSV2. Therefore, if there are many signals to be interfaced between the master chip 110 and the slave chip 120, the number of through chip vias is increased according to the number of signals to be interfaced. This increases the overall size of the semiconductor integrated circuit 100. Moreover, net die may be reduced when the semiconductor chip, herein, the master chip 110, is fabricated.